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怎样改写成三选一多路选择器的VerilogHDL 程序?
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module Maximum_value_detection(baimostlarge,a,b,c,d);output[3:0]Mostlarge;input[3:0] a b,c,d;wire[3:0]sum1,sum2,sum3;assign sum1=(a>daob)?a:b;assign sum2=(c>d)?c:d;assign Mostlarge=(sum1>sum2)?sum1:sum2;endmodule module (clk,rstn,n1,n2,n3,n4,...
直接看输入的bit2和bit3,如果不是00输出为0,否则输出为1。1、module com(a,b);input[3:0]a;output b;assign b=(a>=4'h4)?1:0;endmodule module t_com;reg[3:0]a;wire b;initial begin a=4'h1;5 a=4'h5;5 $stop;end com m(a,b);endmodule 2、module compare(clk, rst_n...